Shared Projects by dewhisna

3-Port MIDI Interface with SMPTE/MTC Display output using STM32F103CB processor.

Display for showing MIDI Time Code. This is similar to the readily available 8-digit 7-segment MAX7219 display module, but has 0.56" display elements instead of 0.36" elements. And it has the digits separated out for “hh:mm:ss.fr” format so that it’s easy to read.

Driver board for a Dual-Resonance Solid-State Musical Tesla Coil. This version replaces the old V2 version, fixing its many errata. This design features a zero-current-switching phase-lead circuit, an over-current detection/lockout circuit, an under-voltage lockout circuit, and a PLL-based adjustable dead-time delay. Requires regulated 24VDC power supply. And is designed to be used with the DRSSTC V2.1 Bridge Board and the DRSSTC Bus Supply V2.

This board adds an interface for a thermal (or other) shutdown (See the DRSSTC Thermal Limiter Board V1 ). It also replaces the UCC37322 driver chips on the V1 board with UCC27423 driven FDD8424H push-pull MOSFET pairs for driving the gate-drive transformers, allowing for much higher current gate drive. And, this board also supports “skip pulse” (or specifically “skip IGBT drive cycle”) mode in addition to the “skip interrupter” mode typically used. This allows harder driving to the over-current detector threshold.

Note: Change RV2 and/or R20 to adjust the SG3525 PLL circuit for your coil’s resonant frequency. With the values of 2K for RV2 and 1K for R20, as labeled, it works for a coil with an approximate resonant frequency of 200-250kHz. Changing them, for example, to 10K for RV2 and 6.8K for R20, it works for a coil that’s approximately 45-100kHz. The exact range is dependent on the dead-time setting, as it alters the frequency slightly, and by component tolerance and circuit parasitics. Refer to the SG3525 datasheet for the frequency equations. Note that FreqOut is 2x the resonant frequency due to the SG3525 dividing the frequency for the dual outputs. The Free-Running frequency of the PLL should be set to about 5% less than 2x the primary circuit resonant.

ERRATA:

1) The outputs from the SG3525 PLL U3 do not feed through the U16 ‘AND’ circuit that merges the ‘Enable’ signal for the output. That means, that on PLL mode, nothing will ever disable the output drive!! That includes both incoming interrupter signal and things like the OCD and UVLO circuits! The simple solution fix is to lift pin 10 of U3 (the SG3525 PLL), which is the ‘shutdown’ pin, so that it’s no longer tied to GND and tie that pin to pin 3 of U6 (the 74LVC1G74 flip/flop), which is the ‘~Enable’ signal. This will shutdown the SG3525 PLL during disable periods (the internal circuit of the PLL is essentially identical to that of the U16 ‘AND’ circuit in this regard).

However, this necessary fix will make it difficult to tune/calibrate the dead-time between the PLL1 and PLL2 outputs of the SG3525, since those outputs will be inherently off most of the time. The “best” bench calibration procedure appears to be to first install the Interrupter Reset Disable jumper and then trigger the fiber optic input with an external light pulse from an interrupter with NO feedback drive into the T1 current transformer (which will keep the ‘Direct’ output of comparator U1, TL3116, deactive). This will release the driver from its initial start-up “lock-out” mode and will keep the lack of interrupter signal from resetting the enable.

Then, use a test-jumper to temporarily short the Anode of D37 (1N4148) and its parallel 1.8K pull-up resistor R50 to ground. That will cause the U6 (74LVC1G74 flip/flop) to set (enter ‘enable’ mode) as if an incoming pulse is seen and will output a low on its pin 3, which will disengage the ‘shutdown’ on the SG3525 (via the newly added jumper) and allow the dead-time between the two outputs to be adjusted. The PLL will then stay running, long enough to calibrate the dead-time adjustment, until something triggers ‘Limit’ or causes a pulse on the ‘Direct’ feedback loop or the Interrupter Reset Disable Jumper is removed, all of which will deactivate the enable.

See also the Updated V2 version of this board which provides SPI display mode support as well.

This board goes inline between a host CPU and an OLED (or similar) I2C graphical display. Its purpose is to convert the graphical display into a character-based display, removing the overhead of font rendering and pixel transfer over the slow I2C bus from the host.

Note that the CPU here is the ATmega328PB (PB version) with dual I2C ports. 12 MHz was chosen for the ceramic resonator, instead of 16MHz or 20 MHz, so that it will run at 3.3v within the specs given in the datasheet. You may, however, be able to overclock it successfully, especially if running at 5v. Be careful, however, of OLED displays with very noisy voltage inverters, as they will interfere with CPU overclocking. I managed to brick two ATmega328PB CPUs trying to run one with this board at 20MHz. 16MHz, however, was no problem.

An identical board with a reversed display connector is also available.

ERRATA: Some I2C displays, like the common SSD1309 2.42" OLED module, require a longer reset pulse than this board currently provides, particularly if the power supply on the display takes a while to settle. If you find your display doesn’t boot correctly, but instead only has a screen garbled with random dots or is otherwise behaving erratically, replace C3 (currently a 0.1uF) with a larger value. It’s recommended to go ahead and make this change during assembly and use a 10uF for C3 of the same ceramic type as C1. During testing, switching C3 from a 0.1uF to a 10uF part has resolved all power-on reset issues encountered.

Driver board for a Dual-Resonance Solid-State Musical Tesla Coil. This version is a mix of the V1 Version and the V2 Version.

This version uses the original UCC37322 drivers (only in the MSOP-PowerPAD footprint instead) and runs on +15V like the V1, but includes the Skip Pulse and thermal limiter input logic from the V2.

The general layout also conforms to the V2 format and is designed to be mounted upright like the V2 instead of upside-down like the V1.

Note: Change RV2 and/or R20 to adjust the SG3525 PLL circuit for your coil’s resonant frequency. With the values of 2K for RV2 and 1K for R20, as labeled, it works for a coil with an approximate resonant frequency of 200-250kHz. Changing them, for example, to 10K for RV2 and 6.8K for R20, it works for a coil that’s approximately 45-100kHz. The exact range is dependent on the dead-time setting, as it alters the frequency slightly, and by component tolerance and circuit parasitics. Refer to the SG3525 datasheet for the frequency equations. Note that FreqOut is 2x the resonant frequency due to the SG3525 dividing the frequency for the dual outputs. The Free-Running frequency of the PLL should be set to about 5% less than 2x the primary circuit resonant.

ERRATA: There is a logic error in the lockout circuit that causes a race-condition with the U9 flip-flop (74LVC1G74) between the fiber-optic edge detect signal on the set-input and the main fiber-optic signal on the clock pin. This can cause the system to never start and results in only a short burst of output at the beginning of each interrupter pulse, and it also prevents the skip-pulse mode from working at all.

To resolve, the fiber optic input signal needs to be removed from pin 1 of U9. And the skip-pulse signal on pin 2 needs to move to pin 1. And pin 2 needs to get tied to +5v. To do this, cut the trace leading into pin 1 of U9 (leaving the 90-degree junction intact where it runs under U4), and cut the trace leading into pin 2 of U9 between U9 and resistor R52. Solder a jumper between pin 1 of U9 and R52, on the end where the trace to pin 2 was cut (this takes care of moving the skip-pulse signal from pin 2 to pin 1). And solder a small jumper wire to pin 2 of U9 that runs to +5v. The closest and probably most convenient point for +5v is the far end of capacitor C40, which is the power decoupling capacitor for U9. This jumper can be quite tricky as it has to solder to a single pin on a TSSOP package (0.65mm pin-spacing).

This errata will be resolved in V3.1.