LVDS Translator ams4005
author: amstark
2 layer board of 0.44 x 0.30 inches (11.1 x 7.6 mm)
Uploaded:
August 24, 2013
Shared:
September 30, 2013
Total Price:
$0.60
LVDS to single ended 3v LVTTL buffer. 3.3v power, gnd, and singled ended signal on one side and LVDS pair on the other. Developed for Virtex 7 FPGA interface. Driver - SN65LVDS1DBVR Receiver - SN65LVDT2DBVR
This design is licensed under the GNU Public License 3.
LVDS to single ended 3v LVTTL buffer. 3.3v power, gnd, and singled ended signal on one side and LVDS pair on the other. Developed for Virtex 7 FPGA interface. Driver - SN65LVDS1DBVR Receiver - SN65LVDT2DBVR
This design is licensed under the GNU Public License 3.
